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LSI Discription

CDP1854A, COP1854AC Types

Initialization

and Controls

In this mode. the CDPJ854A is configured to recei

commands and send stal\Js

via

micro-

processor dat.a bus. The register connected

the transmitter bus

the receiver bus

determined

by the RD/WR and RSEL inputs as follows:

TAB

1-Register

Se•,ct

:;um•nary

RSEL

RD{WR

Function

Low

Load Transmitter Holding Register from Transmitter Bus

LO\\' High Read

Receiv

er Hod

Ung

High

Low

Load Control Register from

Tranm

iltcr

Hus

High

Low Read

Status

In this mode the CDPJ854A is compatible with a bidirectional

s system.

The

receiver and trans·

rnitter buses are connected

the bus. The CLEAR

put

pulsed, resetting

the

Control, Status,

and Receiver Holding Registers

and

setting S.ERIAL DATA OUT(SDO) high. The Control Register

loaded

fron

Trans111itter

Bus

order

to dete

r1nine

the

oper3ting configuration

for

tlu?

UART

Data

transferred from the Transmitter Bus inputs

the

Control Register

ring TPB when the

UART

sel

ected

(CS I · CS2 · CS3

·1

) and the Control Register

designat

(RSEL

= H. RD/

= L

Titc CDPI 854A also has a Status Register wltich can

read

onto

the Receiver Bus

BUS

O-

R BUS

in order to determine the status

the UART. Some

these status bits are also available

at separate te

inals as indi

ted

in Fig. 7.

2. Transmi

Operation

Before beginning to traMmit. the TBANSMIT REQUEST

(TR)

bit in the Control Register (see b

assignment, Fig.

set. Loading the Control Register w

= I (bit 7 =

ihig)

1) inhibits changing

the

othe

r con trol bits. Therefore two loads arc required: one to format the UART, the second

set

1~1ien

has been set, a

ANSMITTER HOLDING REGISTER EMPTY (THRE) inte

rupt will occur. signalling the micropr<icessor that the Transmitter

lding Register

empty

and

may be loaded.

ett

ing

also causes asscrhon of a low

-l

evel

the REQUEST TO SENT

TS)

output

the

peripheral.

is not necessary to set

for proper operation for the UART.

de-

sired, it can

used to enable

THRE

intcrr

~1pts

and to generate the RTS s]gnaL The Transmitter

Holding Regist

loaded from the bus

TPB during exe

cutio

output

. The

CDPI

854A is selected

CS!

•

CS2

•

CS3

and

the

Holding Regis

ter

lected

RSEL =

and

RD/WR =

When the CLEAR

SEND (CTS) input, which

can

be connected

peripheral device

output

, goes low, the Transmitter Shift Register

will

load

ed from the Transmi

t·

ter

lding Register and data transmissi

will

begin.

CTS

always low, the Transm

itte

r Shift

t.he

first high-to.l

edge

the clock which occurs at least 1/2 clock

period after

'the trailing edge

TPll

and

transmi

s.•

a start b

will occur 1/2 clock period

later (see

Fig_

I). Parity (

programmed)

and

stop bit(s) will be transmitted fo

owing

the

last data

bit.

the

word

len

gUt

selected

Jess than 8 bits, the most signifi

nt unused bits in the transmitter

shift register w

ill

not

transmitted.

One tran

smitte

r clock per

d after the Trnnsmitter Shilt Regist

loaded from the Transmitter

Holding Regi

ster

, the THRE signal

will

and an interr

upt

will

occur

(INT

goes low). The next

character to

transmitted can t.hen

loaded

into

the Transmilter Holding Register for trans-

mission

with

its

start

bi!

immediale

following

the

lasl

stop

bit

of t

character.

This

cycle

can

repea

ted

until the l

as!

character

transmitted,

which time a final

THRE

· TSRE

intern

will occur.

T11is

terrupt signals the microprocessor that

can

turned

off. This is done by

not sale this P

DF!!!

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 35 36

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Sharp CE-158 Manuale Utente Pagina 11

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